Soft Error Mitigation Using Prioritized Essential Bits

other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Summary A soft error in configuration memory can corrupt a design. However, the proper operation of a typical design loaded into a Xilinx FPGA only involves a fraction of the total number of configuration memory cells. This application note describes a method for defining the hierarchical regions of interest in a user design and identifying the prioritized essential bits associated with the defined user logic using the ISE® design tools, version 13.4 and later. This application note also describes how the LogiCORE™ IP Soft Error Mitigation (SEM) controller can be used with the prioritized essential bits to detect and correct soft errors in the configuration memory of Xilinx® 7 series and Virtex®-6 FPGAs. The described method reduces the effective failures in time (FIT) and increases design availability. The reference design provided with this document illustrates the design flow.